Memory components contain, as memory medium, a multiplicity of memory cells which form one or more blocks and can in each case store a binary datum (data bit), to be precise by assuming in each case one of two possible cell states, which are usually designated by the logic symbols “0” and “1”. The memory cells in the state of the art are predominantly formed by electrical capacitances or capacitors and store the data by alternative distinguishable charge states, e.g., charged and uncharged. In each of the memory blocks, the memory cells are arranged in the manner of a matrix in rows and columns.
In conventional DRAM components, a plurality (e.g., 23=8) of memory blocks each containing many rows (e.g., 28=256 rows) and columns (e.g., 212=4196 columns) are combined in row-parallel arrangement to form a bank, wherein the component contains a plurality (usually 22=4) of such banks.
In order to write data bits to the cells or read them from the cells, each cell is assigned an individual cell switch via which the cell can be connected to a read/write line. These lines are referred to as bit lines. The cell switches, which are usually formed by field effect transistors and are referred to as selection transistors, can be driven selectively via word lines in order optionally to switch them on (that is to say make them conducting) or to keep them turned off. A respective common word line is provided for each matrix row of a memory block, and a respective common bit line is provided for each matrix column. If a word line is selectively activated, therefore, which is usually effected by a row decoder by the decoding of an externally applied row address, all the cell switches of the relevant row are closed.
This row selection is followed by the column selection, by one or more bit lines of the memory block being selectively connected to assigned data lines leading to an external data connection of the memory component. These connections are usually produced by selectively switching on read/write amplifiers on the bit lines by a column decoder that decodes an externally applied column address.
The word lines pass through the memory block in the row direction, also referred to hereinafter as the “x direction”. The bit lines pass through the memory block in the column direction, also referred to hereinafter as the “y direction”. These two directions are generally (but not necessarily) orthogonal to one another and each run in a plane parallel to the basic area of the semiconductor substrate. The direction pointing perpendicularly to these “horizontal” planes is referred to hereinafter as the “vertical” direction or “z direction”. The expressions “top” (or “over” or “above”) and “bottom” (or “under” or “below”) relate to the spatial position along the z direction, the substrate being “bottommost”.
In general it is desirable to make the horizontal packing density of the components of memory matrices on a chip as high as possible in order to accommodate as many components as possible on a given chip area. One way of increasing the horizontal packing density consists in arranging each memory cell and the assigned selection transistor vertically one above another rather than horizontally alongside one another. Since the channel zone and the drain and source zones of the selection transistors are formed by doping regions of the semiconductor substrate, it is recommended to integrate the memory cells in a level above the transistors.
In a known integration scheme, the selection transistors are shaped in such a way that their drain and source zones representing the “main connections” in each case form elevated regions on both sides of a groove in which is arranged the gate insulated from the bottom and walls of the groove. The gates of all the selection transistors for the respective same matrix row are formed by a common word line which extends in the x direction. The upper edges of the word lines lie below the upper edges of the grooves, and the space of the grooves that remains over the word lines is filled with insulating material, such that the word lines are “buried” in the grooves. The bit lines extending in the y direction are integrated in a level above the selection transistors, with interposition of an insulator layer. Each bit line is connected via vertical conductive feedthroughs to the first main connections of all those selection transistors which are respectively assigned to the same matrix column. The memory cells are integrated in a cell layer above the bit line level, likewise with interposition of an insulator layer. Each memory cell is contact-connected via a vertical conductive feedthrough to the second main electrode of the assigned selection transistor. In order to keep the horizontal extent of the memory cells as small as possible, the cells are shaped in such a way that large constituent parts of them extend in the vertical direction. Therefore, the cell layer is of necessity rather thick.
Since all the selection transistors are formed on the same semiconductor layer, particular measures are needed to decouple spatially adjacent transistors from one another. Particularly good decoupling or isolation is needed in each case between adjacent selection transistors assigned to different columns. For this purpose, it is known to integrate between the selection transistors in each case an “isolation transistor”, which is formed in exactly the same way as the selection transistors and is kept constantly turned off by the application of a suitable gate potential. All isolation transistors oriented along the same row have as gate a common “isolation line”, which is formed in a manner similar to the word lines and runs parallel thereto. All the isolation lines are permanently connected to a source of the reverse-biasing potential mentioned.
It is often desirable to segment a memory block in the row direction, particularly when the rows are very long. The longer a word line, the higher its RC time constant and the longer the duration of the row selection phase, that is to say the time until, after activation of the word line, all selection transistors connected thereto are fully turned on. In order to shorten this response time, it is known per se to subdivide the word lines into individual sections and to drive each section by a separate word line driver. These drivers are connected on the one hand to the assigned word line sections and on the other hand to interconnects which extend in an upper metallization level above the cell layer in the row direction, to be precise over the entire row length.
The segmentation of the word lines of a memory block is difficult if the word lines are buried in the manner described above and in addition buried isolation lines are present. The word line drivers require a relatively large amount of integration area, and all those parts of the drivers which are not contact-connected to the assigned word line must remain decoupled both from the word line and from an adjacent isolation line. It is not known or suggested how this could be achieved without increasing the “pitch” of the word and isolation lines (that is to say the spatial period of the lines in the y direction). Moreover, the question remains open as to via which paths the isolation lines in all their parts should be connected to the permanent reverse-biasing potential.
For these and other reasons, there is a need for the present invention.